1. Field of the Invention
The present invention refers to a method for reconfiguring a memory so as to replace faulty memory cells by non-faulty memory cells in the memory. In particular the present invention refers to a method employing a reconfigurable memory comprising one or more regular (non-redundant) regions with a plurality of memory cells and redundant regions with a plurality of redundant memory cells, the regular regions having a plurality of address lines with assigned memory cells and the redundant regions having a plurality of redundant address lines with assigned memory cells.
2. Description of the Related Art
Modern dynamic semiconductor memories, DRAMs (DRAM=dynamic random access memory=dynamic memory with random access) are all provided with redundant memory cells so as to be able to replace memory cells which are found to be defective during a test run by non-defective functional memory cells. Only so is it possible to produce functional elements or components for new products. A further consequence is that in the case of more mature products there is a dramatic increase in the yield in the manufacture of such products.
Replacement of the memory cells does not take place individually, however, but by means of a readdressing of complete rows or columns of a cell matrix. Boundary conditions as regards the block formation in the replacement regions and the number of redundant rows and columns which are there available must be taken into account here. The attempt to achieve complete coverage, the so-called redundancy analysis, becomes a complicated optimization exercise for complex fault images.
There are no closed solutions in terms of formulae for discovering complete coverage of a given fault image through redundant rows and columns in a memory cell field organized in the form of a matrix. The search for a solution takes the form of checking various reconfigurations, the search being complete if it includes all the theoretically possible reconfigurations. To be efficient, those of the possible reconfigurations which probably provide coverage must be recognized quickly, and the checking sequence must be ordered according to these probabilities. In this way it is possible to reduce astronomically large numbers to just a few actual trial steps in practical cases. Such methods are generally known and do not represent the subject matter of the present invention. These methods are described for example by Chin-Long Wey et al. in IEEE Transactions on Computer Aided Design, Vol. 6, pp. 222–231, 1987.
FIG. 1 shows an example of a matrix-shaped memory cell element of a memory with traditional block-oriented (segmented) redundancy.
The matrix-shaped memory cell field 100 comprises six blocks 102, 104, 106, 108, 110, 112. In each of the blocks 102 to 112 a plurality of individual memory cells is arranged in the form of a matrix; these are addressable via address lines, not shown in FIG. 1, consisting of word lines and bit lines, i.e. they can be called up and activated so as to permit data to be written into them or retrieved from them. In addition each of the blocks 102 to 112 includes three redundant row/word lines 114, 116, 118. Furthermore, each block 102 to 112 includes two redundant column/bit lines 120, 122.
The matrix-shaped memory cell field 100 shown in FIG. 1 possesses traditional block-oriented redundancy. The memory cell field 100 is subdivided into three row blocks, formed by the blocks 102 and 104, 106 and 108, and 110 and 112. The redundant row/word lines 114, 116 and 118 are assigned to the three row blocks. The memory cell field 100 is further subdivided into two column blocks, formed by the blocks 102, 106, 110 and 104, 108, 112.
The redundant word lines 114, 116, 118 can be used in the vertical direction up to the next block boundary 124, 126, 128. In other words, the redundant word lines 114 can be used in the blocks 102 and 104, i.e. in the first row block. Analogously, the redundant word lines 116 and 118 can be used in the row blocks 106, 108 and 110, 112 respectively.
The redundant bit lines 120, 122 can be used in the horizontal direction up to the block boundaries 130 and 132, the redundant bit lines 120 up to the block boundary 130 for the block 102, the block 106 and the block 110, therefore. Analogously, the redundant bit lines 122 can be used for the blocks 104, 108 and 112.
Of decisive importance in the use of the matrix-shaped memory cell field with traditional block-oriented redundancy, described in terms of FIG. 1, and employing a traditional redundancy analyzer is that in the replacement direction of a line type, i.e. of a word line or a bit line, no block boundaries 124 to 132 of the orthogonal line type are transgressed. In the prior art redundancy analyzers are known which reliably find solutions for redundancy architectures wherein the blocks in one direction of the cell matrix completely span one or more blocks in the orthogonal direction, as has just been explained with reference to FIG. 1.
In addition to the memory cell fields with traditional block-oriented redundancy just described, more flexible, so-called blockfree redundancy architectures exist, which offer advantages as regards space needed and the highest possible yield for reparable elements over the approach described in terms of FIG. 1. Such architectures contravene the block formation criterion described in terms of FIG. 1, so that with redundancy analyzers according to the prior art complete fault coverage can no longer be found, even if it exists, for every fault image. The reason for this is that if redundant lines are themselves faulty, the effective fault image is changed by the solution.
The blockfree redundancy architecture will now be explained in more detail with reference to FIG. 2, which shows a matrix-shaped memory cell field 200 with a plurality of blocks 202 to 212 wherein the memory cells of the memory cell field are arranged, address lines (not shown) being assigned to the memory cells. Similarly to the situation in FIG. 1, the memory cell field 200 has a plurality of redundant word lines 214 to 218 and a plurality of redundant bit lines 220 and 222. Block formation for the redundant column/bit lines 220, 222 is indicated by the broken lines 224 and 226. The redundant column/bit lines 220, 222 can be used freely in the horizontal direction at independent addresses in the various blocks, as is indicted schematically by representing the bit lines 220, 222 as interrupted lines. The matrix-shaped memory cell field 200 is formed according to blockfree redundancy, meaning that all nine redundant row/word lines 214 to 218 are freely used in the vertical direction.
The method used for a reconfiguration for replacing faulty memory cells in a memory according to the prior art will now be described in more detail making reference to FIGS. 3A and 3B. According to the present invention, reconfiguration means the readdressing of valid row and column addresses of the regular region of the memory into the redundant region of the memory.
In a first step S300 the memory/memory cell field (including redundant regions) is examined so as to determine faulty memory cells in the memory/memory cell field 200 (fault image). The fault image is stored and in step S302 a first reconfiguration of the available redundant address lines (word and bit lines), which specifies which of the redundant word lines 214 to 218 and/or which of the redundant bit lines 220, 222 should replace fault-afflicted word or bit lines in the individual blocks 202 to 212, is selected by a redundancy analyzer.
In step S304 it is checked whether all the faulty memory cells in the regular region are replaced by this reconfiguration. If this is not the case, a new reconfiguration is specified in step S306 to replace the faulty memory cells and the method then returns to step S304. This loop forms the core of a traditional redundancy analysis method and it is traversed repeatedly until either complete fault coverage is achieved or a termination criterion for the loop is reached and the memory is rejected as being irreparable.
In the check made in step S304 it is assumed that the fault image itself has not been altered by the reconfiguration. This assumption is always fulfilled for traditional block formation (segmentation) according to FIG. 1. For a blockfree redundancy architecture according to FIG. 2, this assumption may prove to be invalid when redundant lines are themselves fault-afflicted. The prerequisite for successful implementation of traditional redundancy analysis methods in conjunction with blockfree redundancy therefore is the guarantee that the replacing rows/columns, i.e. the redundant word lines/bit lines themselves, are fault-free. In reality, however, this assumption will, with a finite probability, prove to be invalid. If faults occur in the redundant section of the memory cell field itself, i.e. if faulty memory cells are assigned to the redundant address lines, an apparent solution offered by a conventional redundancy analyzer may displace faults from the redundant region into the address region of the main cell field and leave them uncovered. This situation results after traversal of the method steps S300 to S304 described in FIG. 3.
To solve this problem, the prior art proposes that, for blockfree redundancy, use of the traditional redundancy analyzer is followed by examination of the emergent solution in respect of faults which have remained uncovered, which can be caused by “migrated” defects on redundant lines. This is represented in FIG. 3 by the step S308. If it is established in step S304 that all faults in the regular region have been replaced, it is established in step S308 whether faulty memory cells from the redundant region have migrated into the regular region. If this is not so, the reconfiguration is output as the solution in step S310. If it turns out that faults have remained uncovered, the memory element is rejected as being irreparable in step S312.
In an expanded method the steps S302 to S308 are regarded as the first solution stage and in a second solution stage it is determined whether the uncovered remaining faults can be covered by means of redundant address lines which have not yet been used. If this is possible, the solution, i.e. the reconfiguration of the memory, is extended accordingly. Otherwise the memory element is rejected as irreparable.
The known two-stage solution method described last is disadvantageous in that the first stage knows nothing of the criteria according to which the second stage operates, so that, in certain circumstances, components/memory elements which are actually reparable are rejected. The reason for this is that analyzer in the first stage can offer a solution which leads to the situation that no further redundant lines are available which would permit coverage of remaining faults on the redundant lines which have been used although an alternative solution would have been possible with which all faults could have been covered. It is desirable that the remaining, theoretically avoidable, yield loss should also be excluded in practice.